In recent years, non-volatile memories of semiconductor devices, in which data is rewritable, are widely used. For example, in flash memories that are typical non-volatile memories, a transistor making up a memory cell has a floating gate or insulation film, also known as a charge storage layer. Data is stored by accumulating charge in the charge storage layer. When the charge is stored in the charge storage layer, a threshold voltage of the transistor is changed. Data is read by reading the threshold voltage of the transistor as a drain current value.
The drain current value is read as follows. Firstly, in a cascode circuit, a bit line connected to a memory cell is precharged. After the bit line is precharged, a cascode circuit converts the drain current into voltage. A sense amplifier compares the converted voltage with a reference voltage to determine whether the data is “0” or “1”. Here, to precharge the bit line means that the bit line is boosted up to a given voltage before the cascode circuit reads the drain current.
FIG. 1 is a circuit diagram of a cascode circuit 100 of a conventional example. A bit line BL is connected to the drain of the transistor making up a memory cell 12 (hereinafter, simply referred to as memory cell). The bit line BL is connected through a pass gate composed of a resistor 101 and a capacitor 102 to a node DATAB. The node DATAB is connected to a differential amplifier circuit 105. The differential amplifier circuit 105 compares a voltage of DATAB with a reference voltage CASREF, and outputs the voltage Vo in proportion to the difference between DATAB and CASREF. Vo is input into the gate of a P-type FET 104 arranged between the node DATAB and the voltage source Vcc.
While the bit line BL is being precharged, if the voltage of DATAB corresponding to the voltage of the bit line BL is lower than the reference voltage CASREF, the voltage Vo becomes lower and the FET 104 supplies current. Accordingly, the bit line BL is charged. If the bit line BL comes to reach the voltage to read the data in the memory cell 12, precharge is completed. At the time of reading the data in the memory cell 12 (that is, reading the current flowing across the memory cell 12), the differential amplifier circuit 105 controls the FET 104 so that the voltage of the bit line BL may be constant. The more the current flows across the memory cell 12, the more the current flows across the FET 104 and the voltage Vo decreases. The less the current flows across the memory cell 12, the less the current flows across the FET 104 and the voltage Vo increases. In this manner, the current flowing across the memory cell 12 is converted into the voltage Vo and the voltage Vo is output to the sense amplifier circuit.
Japanese Patent Application Publication No. 11-149790 discloses a sense amplifier circuit that allows high-speed data reading, by switching on a transistor for precharge at the time of precharging.
In the cascode circuit 100 having the differential amplifier circuit 105 of the conventional example, the differential amplifier circuit 105 is used for precharging and reading data. In order to shorten the data reading time, it is effective to shorten the time necessary for precharging. If the current of the differential amplifier circuit 105 is increased, the time for precharging can be shortened. However, the current for reading the data is increased, thereby increasing the consumption current.